At Hot Chips 2026, Samsung's DRAM design team laid out a three-phase roadmap that progressively turns HBM from a dumb memory stack into a compute-carrying subsystem — and eventually stacks DRAM directly on top of the processor. The numbers matter here: ~70% lower I/O power, roughly 2.3x more DRAM bandwidth, and a 5-10% XPU area reclaim just from moving the memory controller out of the accelerator.

HBM4's 4nm base die is the enabler

The key move is already shipping: starting with HBM4, Samsung moved the HBM base die to a 4nm logic process instead of the DRAM process used for the core dies. That gives the base die the same class of silicon as the XPU itself, which means it can do more than ferry data. The current HBM4 stack delivers 1-5 TB/s across 1,000-2,000 I/Os at 8-16 Gbps each, and scaling that conventionally is getting expensive — power is rising faster than bandwidth.

Phase 1: Reclaim XPU area

The first step evicts non-compute blocks from the accelerators. The HBM PHY is one of the largest blocks on the base die — on an 11 x 12.8mm HBM4 base die, the conventional PHY occupies more than 8 x 4mm. A custom HBM die-to-die link shrinks that to about 8.5 x 1.5mm with channel depth cut from 5.5mm to 2mm. The matching interface on the XPU shrinks too, freeing processor silicon for compute.

Samsung's Han estimated the memory controller accounts for 5-10% of an XPU's area. Moving it into the base die could yield a 10-20% performance gain when that space is refilled with compute. They also proposed an SRAM-based repair scheme that redirects failed C-die addresses to SRAM on the base die — avoiding the waste of a full spare row for a single defective cell.

Shrinking the same power into less silicon creates hotspots. Samsung's answer is a Heat Path Block (HPB) that covers more than half the PHY and can slash peak temperature by more than 35%.

Phase 2: Smart memory subsystem

Phase 2 fills the remaining base-die area with more functions. Samsung proposes SoC-like telemetry, including thermal, voltage, process, and aging sensors plus enhanced self-test. The base die's edge can host direct memory expansion — dedicated controllers and PHYs connecting a secondary tier of LPDDR or even HBM without going through PCIe. That's higher bandwidth and lower latency than PCIe-based memory extension.

Then comes compute on the base die. Selected processing elements sit under the DRAM, offloading memory-bound work while compute-heavy operations stay on the GPU. Samsung calls this broader 2.5D architecture advanced HBM (aHBM): less traffic across the interposer, lower latency, reduced I/O power.

Phase 3: zHBM goes fully 3D

zHBM is the radical step: the processor sits directly beneath the DRAM stack. No interposer, no conventional edge PHY, no D2D links. Distributed I/Os spread across the whole die replace the large edge PHY, and data no longer travels laterally.

The payoff is power. Samsung projects zHBM cutting I/O power by around 70% compared with HBM5. In one modeled example, that's roughly 2.3x more DRAM bandwidth while reducing memory power by about 100W versus a four-stack HBM4E system.

The tradeoff is heat. Samsung targets roughly four-high zHBM stacks versus the 12-high or 16-high conventional HBM allows — precisely because of thermal limits. Manufacturing requires advanced wafer-on-wafer and hybrid copper bonding, plus much tighter co-design between DRAM and SoC teams.

What this means for you

Samsung gave no firm launch dates. HBM4's 4nm base die is the concrete starting point; cHBM and aHBM are nearer-term extensions with zHBM as the long-term endpoint.

For anyone running local inference, the relevant horizon is the next solid step, not zHBM itself. When the memory controller leaves the accelerator die, every future GPU and NPU devotes that silicon to compute. When memory-bound operations can run inside the base die, a meaningful fraction of what today forces you onto a PCIe bus or NVLink disappears.

I would not change any buying decision on this roadmap. There is no benchmark for a chip Samsung has not shipped, and the 2026 HBM supply situation remains far more pressing — DRAM prices have already spiked hard. What zHBM tells us is directional: the memory wall is the binding constraint on inference cost and power, and every vendor is attacking it from inside the memory stack.

Phase Architecture Key change Stated benefit
1 cHBM PHY shrinks, memory controller moves into base die 5-10% XPU area reclaimed; 10-20% perf gain
2 aHBM Telemetry, direct external memory, PEs under DRAM Lower latency, less interposer traffic
3 zHBM DRAM stacked on processor, distributed I/Os ~70% I/O power cut vs HBM5; ~2.3x bandwidth

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